1. Field of the Invention
The present invention relates generally to taped semiconductor devices. The invention also relates to methods of making taped semiconductor devices.
More particularly, the invention relates to a method of making leads on chip (LOC) semiconductor devices with ball grid arrays (BGA).
2. Discussion of the Related Art
A known LOC device is shown in U.S. Pat. No. 5,391,918 (Koyanagi et al.). The Koyanagi device has leads located above a semiconductor chip. The leads are separated from the chip by an insulating layer. The leads are connected by wires to bond pads in the center of the chip. The chip, the leads and the wires are encapsulated in a resin package.
The Koyanagi device has a number of disadvantages. One disadvantage is that the leads can be formed on only one chip at a time. To produce the Koyanagi device, the chip must be singulated from a wafer before the leads are formed. There is a need in the art for an improved method of forming leads on unsingulated chips.
Another disadvantage with the Koyanagi device is that the leads extend laterally beyond the side edges of the chip. The lateral dimensions of the leads are substantially greater than those of the chip. Consequently, the Koyanagi device cannot make efficient use of all of the available space on a printed circuit board.
U.S. Pat. No. 5,218,168 (Mitchel et al.) describes a semiconductor device with metal leads formed in a polyimide film. Solder beads connect the leads to respective die circuits and a lead frame. The beads extend through via holes in the polyimide film. A disadvantage with the Mitchell device is that the leads are not applied to the die circuits until after the circuits are diced out of a wafer. The leads are applied separately to singulated semiconductor chips.
Another disadvantage with the Mitchell device is that the lead frame extends beyond the side edges of the chip. Consequently, the area occupied by the finished device is substantially greater than the area available for circuitry on the chip. Since the periphery of the chip is inside the ends of the leads, the Mitchell device cannot fully utilize space on a printed circuit board.
Another disadvantage with the Mitchell device is that high temperature is used to adhere the polyimide film to the semiconductor chip. The high temperature may cause the film and the chip to expand at different rates, which causes misalignment problems.
The disadvantages of the prior art are overcome to a great extent by the present invention. In one aspect of the invention, a multi-layer tape is applied to a semiconductor wafer, before the wafer is diced into chips. The tape has a slot-shaped opening for each chip in the wafer. Electrically conductive leads are printed on the tape. Bond wires extend through the openings and connect the chips to the leads. The wires are glob top encapsulated in resin, and ball grid arrays are deposited on the leads. The ball grid arrays are located above the chips, within the respective peripheries of the chips.
In another aspect of the invention, the tape has a dielectric layer, and an adhesive layer is used to connect the dielectric layer to the wafer. Preferably, the adhesive layer is formed of low temperature curing adhesive material. In a preferred embodiment, the adhesive material achieves ninety percent of its maximum strength in less than about thirty six hours at seventy five degrees Fahrenheit. Consequently, it can be cured at room temperature. The low temperature curing adhesive material avoids misalignment problems that would be caused by a heat activated adhesive.
The adhesive layer may be stenciled onto the wafer before the tape is applied. Alternatively, the adhesive layer is applied to the tape first, and then the adhesive/tape matrix is applied to the wafer. In either event, the tape may be accurately adhered to multiple chips in a single alignment step.
The present invention also relates to a method of making semiconductor devices. The method employs a tape having a dielectric layer and electrically conductive leads. The tape may be stored on a roll. The tape is adhered to the wafer at room temperature to avoid alignment problems caused by differential thermal expansion. Bond wires are formed to connect the integrated circuits on the wafer to the electrically conductive leads.
In another aspect of the invention, the ball grid arrays are formed on the leads before the circuits are diced out of the wafer. This has the advantage of providing solder balls on a large number of devices at the same time. AU of the balls may be formed during a single processing step. In addition, by locating the balls on the leads, inside the periphery of the respective chip, the lateral dimensions of the completed device are no larger than those of the chip. Consequently, space utilization on a printed circuit board is improved. In other words, the amount of chip circuitry and/or memory can be increased per unit area of occupied printed circuit board.
The individual chips may be separated from the wafer by dicing or sawing. During the singulation process, the tape provides mechanical protection for the integrated circuits, and the glob top resin protects the bond wires and the connections at the ends of the bond wires.
In an alternative embodiment of the invention, anisotropically conductive adhesive material is used to form a taped device. In this embodiment, bond wires are replaced by metal located in via holes in the dielectric layer. The anisotropically conductive adhesive material provides electrical connections between the via holes and the bond pads on the chip. The metal in the via holes is integrally connected to leads printed on the tape. A ball grid array is formed on the leads.
These and other features and advantages of the invention will become apparent from the following detailed description of preferred embodiments of the invention.